The invention relates to bit switch circuitry associated with R/2R ladder voltage divider networks used in digital-to-analog converters (DACs).
The closest prior art is believed to be FIGS. 5 and 9 of U.S. Pat. No. 5,764,174 (Dempsey et a.), in which V.sub.gp and V.sub.gn of FIG. 9 are provided as controlled "supply" voltages to CMOS buffers 116i and 118i of FIG. 5. U.S. Pat. No. 5,075,677 (Meaney et al.) and U.S. Pat. No. 4,558,242 (Tuthill et al.) also disclose prior art circuits for switching the 2R shunt resistors of R/2R ladders to high and low reference voltages.
The control circuit of FIG. 9 of the Dempsey et al. patent generates two control voltages V.sub.gp and V.sub.gn which are applied as supply voltages for a pair of CMOS inverters or buffers 46.sub.i and 48.sub.1, respectively. The CMOS buffers 46.sub.i and 48.sub.i are controlled by a binary input b.sub.i to turn MOSFETs 42.sub.i and 44.sub.i on and off. The drain electrodes of MOSFETs 42.sub.i and 44.sub.i are connected to a corresponding leg of an R/2R ladder network. MOSFET 42.sub.i can be either P-channel or N-channel (See FIG. 6 of the Dempsey et al. patent), and buffer 46.sub.i is correspondingly inverting or non-inverting.
The operational amplifiers 58 and 59 each operate to balance their (+) and (-) inputs. Resistors 54 and 57 in FIG. 9 of the Dempsey et al. patent establish the same bias currents, in order to match the on resistance of combined MOSFETs 55 to the resistance of combined resistors 52, and match the on resistance of combined MOSFETs 56 to the resistance of combined resistors 53. The circuit structure which produces the common bias currents includes resistors 54 and 57 and prevents accurate operation of the circuit of FIG. 9 of the Dempsey et al. patent if v.sub.REF+ is not more than approximately 2 volts above V.sub.REF-. As the difference between V.sub.REF+ and V.sub.REF- decreases, the current through the circuit of FIG. 9 decreases, and the offset errors of the two operational amplifiers become increasingly large proportions of the voltage drops across the resistors. This leads to increasingly large inaccuracies in operation.
FIG. 11 of the Dempsey et al. patent discloses an alternative embodiment in which unit resistors 72 and 74 are connected in series between the drains of the MOSFET switches 42.sub.i and 44.sub.i and the corresponding leg of the R/2R ladder. This embodiment controls the on resistance of the MOSFET switches 42.sub.i and 44.sub.i with respect to the resistances of unit resistors 72 and 74.
The control and switching circuitry of the Dempsey et al. patent and all of the relevant prior art is designed to be used in conjunction with conventional R/2R resistive divider networks in which the series resistors all have the resistance R and the shunt resistors all have the resistance 2R.
For all known R/2R resistive divider networks, it is necessary to binarily scale the channel-width-to-channel-length ratios (W/L ratios) of the switches that selectively couple the 2R shunt resistors to the high reference voltage or the low reference voltage. This is very problematic for digital-to-analog converters having a large number of bits of resolution, e.g., 12 to 16 bits of resolution. For example, in a 16-bit digital-to-analog converter, if the on resistance of the MSB switch is 40 ohms, the on resistance of the LSB switch would be 320 kilohms to 1.20 megohms. Very large MOSFETs are required to provide a 40 ohm on resistance because the channel width W must be very large. Very large MOSFETs are also required to provide an on resistance of 320 kilohms to 1.20 megohms because the channel length L must be very large. Therefore, a large amount of chip area is required for an accurate implementation of a digital-to-analog converter using an R/2R divider network. To avoid the large amount of chip area, those skilled in the art have developed various "short cuts" for avoiding the use of very large MOSFET switches for the LSB bits, but these techniques introduce inaccuracies that may not be acceptable for digital-to-analog converters having more than about 12 bits of resolution.
For example, in some cases those skilled in the art simply do not binarily scale the size of the switches for the least significant bits of the R/2R ladder and merely accept the resulting errors. Another approach has been to insert a high resistance thin-film resistor in series with the switch, and accept the fact that the temperature coefficient of the thin-film resistor is different than that of the on resistance of the switch. Using unit resistors as shown in FIG. 13 of the Dempsey et al. patent is yet another shortcut that has been used to avoid binarily scaling the on resistances of the switches for the least significant legs of an R/2R ladder network.
A difficulty in scaling MOSFET switches to have large on resistances by making the channel length L very long is that the magnitude of the effective gate-to-source voltage which produces the on resistance R.sub.ON is progressively reduced along the length of the channel region due to a voltage drop developed along the channel region due to current flowing through it. Consequently, binarily scaling the W/L ratio does not result in binarily scaling R.sub.ON for all values of channel current. This causes code-dependent errors, especially in the least significant bit switches, because the channel currents are very code-dependent in MOSFET switches connected to an R/2R ladder. This is a major problem in obtaining high resolution digital-to-analog converters of high accuracy.
It would be very desirable to provide a digital-to-analog converter (1) which is more accurate than those of the prior art, and (2) in which the difference between the externally supplied upper and lower reference voltages can be small.